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| SSM4957(G)M DUAL P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement Lower gate charge Fast switching characteristics D1 D2 D1 D2 BV DSS R DS(ON) ID G2 S2 -30V 24m -7.7A SO-8 G1 S1 Description Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM4957M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for low-voltage applications. G1 D1 D2 G2 S1 S2 This device is available with Pb-free lead finish (second-level interconnect) as SSM4957GM. Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=100C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating -30 20 -7.7 -6.1 -30 2 0.016 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit C/W 10/21/2004 Rev.1.01 www.SiliconStandard.com 1 of 5 SSM4957(G)M Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=-250uA 2 Min. -30 -1 - Typ. -0.02 12 27 5 18 14 11 38 25 530 435 Max. Units 24 36 -3 -1 -25 100 45 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA Static Drain-Source On-Resistance VGS=-10V, ID=-7A VGS=-4.5V, ID=-5A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=-250uA VDS=-10V, ID=-7A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS=20V ID=-7A VDS=-24V VGS=-4.5V VDS=-15V ID=-1A RG=3.3 , VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1670 2670 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 2 Test Conditions IS=-1.7A, VGS=0V IS=-7A, VGS=0V, dI/dt=100A/s Min. - Typ. 35 34 Max. Units -1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135C/W when mounted on min. copper pad. 10/21/2004 Rev.1.01 www.SiliconStandard.com 2 of 5 SSM4957(G)M 120 120 100 T A = 25 C -7.0V -ID , Drain Current (A) o -10V 100 T A = 150 C o -10V -ID , Drain Current (A) 80 80 -7.0V 60 60 40 -5.0V -4.5V 40 -5.0V -4.5V V G =-3.0V 20 20 V G =-3.0V 0 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 48 1.6 ID=-5A T A =25C 40 1.4 ID=-7A V G =-10V Normalized R DS(ON) RDS(ON) (m ) 1.2 32 1.0 24 0.8 16 0.6 3 5 7 9 11 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.0 7 6 1.5 5 -IS(A) 4 T j =150 o C 3 T j =25 o C Normalized -VGS(th) (V) 1.0 2 0.5 1 0 0 0.2 0.4 0.6 0.8 1 1.2 0.0 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 10/21/2004 Rev.1.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM4957(G)M 12 10000 f=1.0MHz -VGS , Gate to Source Voltage (V) 10 ID= -7A V DS = - 24 V C iss 8 6 C (pF) 1000 4 C oss C rss 2 0 0 10 20 30 40 50 60 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 0.2 10 0.1 0.1 1ms -ID (A) 1 0.05 10ms 100ms 0.02 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135oC/W 0.1 T A =25 o C Single Pulse 0.01 0.1 1 10 1s DC 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 10/21/2004 Rev.1.01 www.SiliconStandard.com 4 of 5 SSM4957(G)M Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/21/2004 Rev.1.01 www.SiliconStandard.com 5 of 5 |
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